A typical semiconductor memory device includes a plurality of memory cells arranged in arrays, and a memory cell selector means for enabling the selection of a particular memory cell to facilitate the reading of data from, or the writing of data to, that particular memory cell.
For example, a high density dynamic random access memory (DRAM) includes a plurality of core cell blocks, and each core cell block contains several memory cells. The memory cells are metal-oxide semiconductor field-effect transistors (MOSFETs), and each MOSFET acts as a switch. To this end, each pair of MOSFETs is connected to a pair of bit lines (an input/output or I/O port), and the capacitance of each MOSFET can be charged by data.
A bit line sense amplifier is provided in communication with each I/O port corresponding to each pair of memory cells. Each bit line sense amplifier amplifies the data which is read from, or the data which is transferred to, the corresponding MOSFET or memory cell through the bit line pair or I/O port.
To select a memory cell, a memory column address is provided to the DRAM from outside the DRAM. A column decoder decodes this column address which is received from outside the DRAM, and then provides a signal to the corresponding bit line sense amplifier to select the proper bit line of the bit line pair or I/O port therefore selecting the corresponding memory cell which corresponds thereto.
A typical DRAM provides that each column decoder decodes four columns, two columns from each side of a core cell block, where each column contains one bit line sense amplifier corresponding to one I/O port (bit line pair). An input/output bus line, which is an input/output data line that sends data to a write (data-in) buffer, is driven by four column decoders. Therefore, the bus line of a typical DRAM is sixteen columns wide.
In many situations, data bit organizations are not extremely wide. Therefore, each column decoder will produce four columns of data, and the above-described DRAM structure, where each column decoder decodes four columns and each bus line is sixteen columns wide, is effective and acceptable.
In contrast, in many other situations, such as where the DRAM is embedded on an ASIC chip with other memory structures, the data bit organization is much wider. As a result, the above-described conventional DRAM bit line structure, where each column decoder decodes four columns, provides much disadvantage. Therefore, within many embedded DRAM applications, an input/output scheme similar to that of an SRAM is utilized.
Such a DRAM structure provides that several core cell blocks are placed in parallel. Of course, the number of rows within each core cell block will depend upon the memory size to be provided. Each column port has two gates, and while one gate corresponds to a column decoder, the other gate corresponds to an "n.sub.-- sen" signal produced from nsg (N sense gate signal)--a delayed gating signal produced by a corresponding bit line sense amplifier.
This DRAM structure is acceptable for some embedded DRAM applications. However, some embedded DRAM applications, as DRAM users and system engineers generally are aware, must utilize a parity bit. This DRAM structure does not generally provide for the implementation of a parity bit without having to utilize an extra column decoder. For example, it is not easy to provide parity bit organizations such as `x9`, `x17`, `x18`, `x34`, `x36`, `x68`, `x72`, `x136`, `x144`, and so on, in a tight column pitch within a DRAM which only utilizes column decoders which decode four columns. The extra column for the parity bit requires that the next column decoder be used.